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Integrated Circuit Systems, Inc.
ICS9159C-14
Frequency Generator and Integrated Buffer for PENTIUMTM
General Description
The ICS9159C-14 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium, PowerPC,TM etc. Four different reference frequency multiply-ing factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific applications. It has a TURBO pin that can speed up the 60 and 66.6 MHz clocks by 2.5%. High drive BCLK outputs provide typically greater than 1V/ ns slew rate into 30pF loads. PCLK outputs provide typically better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle. * * * * * *
Features
Generates up to four processor and six bus clocks, plus disk, USB and reference clocks Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs TURBO input pin that can speed up the 60 and 66.6 MHz PCLKs by 2.5%. 2.5V or 3.3V output: PCLK (0:3) 3.0V - 5.5V supply range 28-pin SOIC package
Block Diagram Pin Cnfiguration
28-Pin SOIC Functionality
TURBO FS1 FS0 X1, REF (MHz) PCLK (MHz)
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
50 66.8 60 55 83.3 68.4 61.6 75
PCLK(0:3) VCO/2
BCLK(0:5) PCLK/2
USB 48 MHz
DISK 24 MHz
All frequencies in MHz, assuming 14.318 MHz input.
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of Motorola Corporation.
ICS9159C-14RevC062397P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9159C-14
Pin Descriptions
PIN NUMBER 1, 26 PIN NAME TYPE DESCRIPTION
VDD X1 X2 VSS TURBO PCLK(0:3) VDD2 FS(0:1) VDD BCLK(0:5) DISK USB REF(0:1)
PWR IN OUT PWR IN OUT PWR IN PWR OUT OUT OUT OUT
2 3 4, 11, 17, 23 5 6, 7, 9, 10 8 13, 12 14, 20 15, 16, 18 19, 21, 22 24 25 28, 27
Power for logic and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. XTAL output which includes XTAL load capacitance. Ground Speeds up the 60 and 66.6 MHz by 2.5% (see functionality table). It has an internal pull-up resistor. Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. Power for PCLK output buffers only. This VDD supply can be reduced to 2.5V for PCLK (0:3) outputs. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. Power for BCLK output buffers. Busclock outputs are fixed at one half the PCLK frequency. The DISK controller clock is fixed at 24 MHz (with 14.318 MHZ input) The USB clock is fixed at 48 MHz (with 14.318 MHz input). REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz.
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ICS9159C-14
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND -0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0C to +70C Storage Temperature ........................................................................... -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current 1 Output High Current 1 Output Low Current 1 Output High Current
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 0.7VDD
TYP -10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 55
MAX 0.2VDD 5.0 -42.0 -30.0 0.4 0.4 110
UNITS V V mA mA Ma mA mA mA V V V V mA
VIN=0V VIN=VDD VOL=0.8V; for PCLKs & BCLKs VOH=2.0V; for PCLKs & BCLKs VOL=0.8V; for fixed CLKs VOH=2.0V; for fixed CLKs IOL=15mA; for PCLKs & BCLKs IOH=-30mA; for PCLKs & BCLKs IOL=12.5mA; for fixed CLKs IOH=-20mA; for fixed CLKs @66.5 MHz; all outputs unloaded
-28.0 -5.0 30.0 25.0 2.4 2.4 -
Output Low Voltage 1 Output High Voltage 1 Output Low Voltage 1 Output High Voltage Supply Current
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-14
Electrical Characteristics at 3.3V
VDD = 3.1 - 3.7 V, TA = 0 - 70 C
PARAMETER
Rise Time
1
Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma Jitter, Absolute1 Input Frequency1 Logic Input Capacitance 1 Crystal Oscillator Capacitance1 Power-on Time1 Frequency Settling Time 1 Clock Skew Window 1 Clock Skew Window 1 Clock Skew Window 1
1
AC Characteristics SYMBOL TEST CONDITIONS 20pF load, 0.8 to 2.0V Tr1 PCLK & BCLK 20pF load, 2.0 to 0.8V Tf1 PCLK & BCLK 20pF load, 20% to 80% Tr2 PCLK & BCLK 20pF load, 80% to 20% Tf2 PCLK & BCLK Dt 20pF load @ VOUT=1.4V PCLK & BCLK; Tj1s1 Load=20pF. PCLK & BCLK; Tjab1 Load=20pF. Tj1s2 Fixed CLK; Load=20pF Tjab2 Fixed CLK; Load=20pF Fi CIN Logic input pins
MIN
TYP
MAX
UNITS
48 -250 -5 12.0 1
0.9 0.8 1.5 1.4 50 50 1 2 14.318 5 18 2.5 2.0 150 300 2.6
1.5 1.4 2.5 2.4 58 150 250 3 5 16.0 4.5 4.0 250 500 5
ns ns ns ns % ps ps % % MHz pF pF ms ms ps ps ns
CINX ton ts Tsk1 Tsk2 Tsk3
X1, X2 pins From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-14
Electrical Characteristics at 5.0V
VDD = 4.5 - 5.5 V, TA = 0 - 70 C
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current 1 Output Low Current1 Output High Current
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 2.4
TYP -15 62.0 -152 50.0 -110.0 0.25 4.0 0.2 4.7 80.0
MAX 0.8 5.0 -90.0 -65.0 0.4 0.4 160.0
UNITS V V A A mA mA mA mA V V V V mA
VIN=0V VIN=VDD VOL=0.8V; for PCLKs & BCLKs VOL=2.0V; for PCLKs & BCLKs VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL=20mA; for PCLKs & BCLKs IOH=-70mA; for PCLKs & BCLKs IOL=15mA; for fixed CLKs IOH=-50mA; for fixed CLKs @66.5 MHz; all outputs unloaded
-45 -5.0 36.0 30.0 2.4 2.4 -
Output Low Voltage1 Output High Voltage 1 Output Low Voltage1 Output High Voltage 1 Supply Current
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-14
Electrical Characteristics at 5.5V
VDD = 4.5 - 5.5 V, TA = 0 - 70 C
PARAMETER Rise Time
1
Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 Input Frequency1 Logic Input Capacitance1 Crystal OscillatorCapacitance1 Power-on Time1 Frequency Settling Time1 Clock Skew Window 1 Clock Skew Window 1 Clock Skew Window 1
AC Characteristics SYMBOL TEST CONDITIONS 20pF load, 0.8 to 2.0V Tr1 PCLK & BCLK 20pF load, 2.0 to 0.8V Tf1 PCLK & BCLK 20pF load, 20% to 80% Tr2 PCLK & BCLK 20pF load, 80% to 20% Tf2 PCLK & BCLK Dt1 20pF load @ VOUT=1.4V Dt2 20pF load @ VOUT=50% PCLK & BCLK; Tj1s1 Load=20pF, Rs=33 PCLK & BCLK; Tjab1 Load=20pF, Rs=33 Tj1s2 REF CLKs; Load=20pF Rs=33 Tjab2 REF CLKs; Load=20pF Rs=33 Fi CIN Logic input pins
MIN 50 45 -250 -5 12.0 1
TYP 0.55 0.52 1.2 1.1 57 50 50 1 2 14.318 5 18 2.5 2.0 150 300 2.6
MAX UNITS 0.95 0.90 2.1 2.0 60 55 150 250 3 5 16.0 4.5 4.0 250 500 5 ns ns ns ns % % ps ps % % MHz pF pF ms ms ps ps ns
CINX ton ts Tsk1 Tsk2 Tsk3
X1, X2 pins From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK & BCLK; Load=20pF; @1.4V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-14
LEAD COUNT DIMENSIONL
28L 0.704
SOIC Package Ordering Information
ICS9159CM-14
Example:
ICS XXXX M-PPP
Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS=Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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